In manufacturing semiconductor memory devices, the memory devices are generally screened prior to shipping by revealing latent failures of the memory devices. During screening, those memory devices having the possibility of initial failure are removed to ensure the reliability of the shipped semiconductor memory devices. One of such screening methods is accelerated stress testing, in which the memory devices are subjected to one or more of extreme electrical, environmental or other conditions for a period of time. An exemplary form of accelerated stress testing is "burn-in" testing, in which high temperature and high voltage are applied to a semiconductor device. During burn-in testing, a semiconductor device is operated with the applied voltage higher than a voltage applied in normal operation and with the ambient temperature higher than a temperature normally experienced, so that the semiconductor device experiences, within a very short period of time, stress greater than that caused during the initial failure period under practical conditions. Such screening efficiently identifies those semiconductor devices likely to experience infant mortality and thus improves the reliability of surviving devices.
To be effective, accelerated stress testing should be comprehensive in the sense that every node of a device should be tested while in a 0 state and a 1 state. In a semiconductor memory device with a large storage capacity, this requirement of comprehensiveness can cause the testing to take a very long time unless special testing accommodations are made. In the normal operation of a RAM (random access memory) device, each unique combination of input address lines activates, via an address decoder, a different word line, which accesses a different word in a memory array. Accelerated stress testing in the normal mode of operation requires that each different address be asserted sequentially (so called "address scanning"); at each address, an all-0 pattern is read and/or written, followed by an all-1 word (or possibly different pairs of complementary patterns). If the time required for effective accelerated stress testing of each node were X seconds, and the memory device contains Y words, then the total time for testing would be XY seconds. Because modem memory devices contain as many as 8,192 words or more, testing in the normal mode of operation is prohibitively time consuming. For example, if X=3 seconds and Y=8,192, the required testing time is nearly seven hours per device.
To reduce the time needed for accelerated stress testing of a memory array, it is known in the art to design the memory device to have a testing capability such that all word lines can be simultaneously activated. In this way, the entire decoder can be tested in one pass. However, this technique is not useful for accelerated stress testing of circuitry peripheral to the memory array, such as address decoders, which are speed critical. This problem is all the more poignant in a memory device designed for speedy access, such as a memory device intended for use as a cache to a microprocessor. In such cases, fast access is attributable to the address decoders and other peripheral circuitry rather than the memory array, and burn-in testing of the peripheral circuitry is especially important. Adding logic enabling the simultaneous activation of all word lines slows the address decoding and hence the memory system.